This invention relates to an event based semiconductor test system for testing semiconductor devices, and more particularly, to a method and apparatus for generating test patterns and strobe signals based on event data in which a delay time can be easily inserted in event data of a specific event without affecting the other events.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. The present invention is directed to such an event based semiconductor test system.
In an event based test system, notion of events are employed, which are any changes of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. The timings of the events are defined with respect to a time length from a reference time point. Typically, such a reference time point is a timing of the previous event. Alternatively, such a reference time point is a fixed start time common to all of the events.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc. at each and every test cycle, the description of the timing data can be dramatically simplified. In the event based test system, as noted above, typically, the timing (event) data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events (delta time) is small, unlike a time difference from a fixed start point (absolute time), a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
For producing high resolution timings, the time length (delay value) between the events is defined by a combination of an integer multiple of a reference clock cycle (integer part or event count) and a fraction of the reference clock cycle (fractional part or event vernier). A timing relationship between the event count and the event vernier is shown in timing charts of FIGS. 3A-3E. In this example, a reference clock (master clock or system clock) of FIG. 3A has a clock cycle (hereafter also referred to as xe2x80x9cperiodxe2x80x9d or xe2x80x9ctime intervalxe2x80x9d) T. Event 0, Event 1 and Event 2 are related in timings as shown in FIG. 3C.
To describe Event 1 with reference to Event 0, a time difference (delay) xcex94V1 between the two events is defined in an event memory. The timing of Event 2 is defined by a time difference (delay) xcex94V2 from Event 1. Similarly, the timing of Event 3 in FIG. 3E is defined by a time difference (delay) xcex94V3 from Event 2. In the event test system, the timing data in the event memory is read out and summed up to all of the previous events to produce an ultimate timing of the current event.
Therefore, in the example of FIG. 3C, to produce Event 1, the timing relationship of FIG. 3B is used in which N1T denotes the event count which is N1 times of the reference clock period T and xcex941T denotes the event vernier which is a fraction of the reference clock period T. Similarly to produce Event 3 in FIG. 3E with reference to Event 0, the timing data for all prior events are summed up to produce an overall time difference expressed by N3T+xcex943T wherein N3T denotes the event count which is N3 times the reference clock period T and xcex943T denotes the event vernier which is a fraction of the reference clock period T.
In actual device testing, a test signal for a certain pin of the device under test may not change for a long period of time such as several hundred milliseconds while test signals for most other pins change at much higher rates such as several ten or hundred nanoseconds. This means that the time length between the two adjacent events is in a very wide variety, requiring large bits of data to describe the maximum possible time length. Since a semiconductor test system is a large system having, for example, several hundred test channels (pins), where each test channel includes an event memory, it is desirable to minimize the capacity of the event memory to decrease the overall cost of the test system.
Therefore, it is an object of the present invention to provide an event based semiconductor test system and event generation method therein for inserting a delay time in timing data of a specified event for enlarging a time difference between two events without affecting the operation of the test system.
It is another object of the present invention to provide an event based semiconductor test system and event generation method therein for producing series of events of various timings wherein an event memory stores the timing data with use of relatively small number of data bits for expressing both long and short time differences between the events.
It is a further object of the present invention to provide an event based semiconductor test system and event generation method therein for producing an event based on a delta time (time difference) from the previous event by storing and modifying the timing data in an event memory of a small memory capacity.
The present invention is an event based test system for testing an electronics device under test (DUT) by producing events of various timings for supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The timings of the events can be freely changed by changing the timing data in an event memory. Such an event memory has a relatively small capacity and a short word length even, for storing the timing data of a large time difference between two events.
In the present invention, the apparatus for generating test patterns and strobe signals based on event data is comprised of an event memory for storing timing data and event type data of each event wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and means for inserting a delay time in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory, wherein the means for inserting the delay time includes means for replicating the timing data and the event type data of the event immediately prior to the specified event.
In another aspect of the present invention, the means for inserting the delay time includes means for inserting a NOP (NO-Operation) event indicating an additional delay time to be added to the specified event and a NOP (NO-Operation) as the event type data, thereby inserting the additional delay time without performing any operations by the test system. The present invention also involves a method of inserting the delay time in the timing data for producing the sequence of events.
In the first and second aspects of the present invention, the timing data in the event memory is comprised of delay count data which is formed with an integer multiple of a reference clock period (integral part data) and delay vernier data which is formed with a fraction of the reference clock period (fractional part data). Further in the first and second aspects of the present invention, such insertion of delay time is repeated multiple of times to attain the desired total delay time of the current event.
A further aspect of the present invention is a method of inserting a delay time in timing data of events to be used for testing semiconductor devices. The method is comprised of the steps of storing timing data and event type data of each event in an event memory wherein the timing data of a current event is expressed by a delay time from an event immediately prior thereto with use of a specified number of data bits, and inserting a delay time in the timing data of a specified event in such a way to establish a total delay time of the current event which is longer than that can be expressed by the specified number of data bits in the event memory. The delay time inserting step is performed by either replicating the timing data and the event type data of the event immediately prior to the specified event or inserting a NOP (NO-Operation) event indicating an additional delay time to be added to the specified event and a NOP (NO-Operation) as the event type data, thereby inserting the additional delay time without performing any operations by the test system.
According to the present invention, the event based semiconductor test system is capable of producing the events of various timings based on the event data stored in the event memory to evaluate the semiconductor device. The timing of each of the events is defined by a difference of time length (delta time) from the last event. The delta time between events can be easily enlarged by inserting a delay time therein in a manner that an overall delta time after the delay time insertion is greater than the maximum word length of the event memory. In one aspect, the delay time insertion operation in the event test system of the present invention is performed by repeating an event immediately prior to the current event until reaching the desired time length. In another aspect, the delay time insertion operation in the event test system is performed by invoking a NOP (no-operation) for the current event until reaching the desired time length.